1. Field of the Invention
The present invention relates to electrical devices, e.g., semiconductor integrated circuit devices, having inlaid (“damascene”-type) metallization patterns, and to a method for reliably reducing parasitic capacitance between adjacent metal features. More specifically, the present invention relates to semiconductor devices comprising copper interconnection patterns and is applicable to manufacture of high speed integrated circuits having sub-micron dimensioned design features and high electrical conductivity interconnect structures.
2. Description of Related Art
There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to a steady reduction in separation between conductive lines in order to reduce integrated circuit size and/or increase density. The reduced spacing between the conductive lines has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines. This produces a phenomenon known as capacitive crosstalk.
In the past, overall integrated circuit (IC) performance depended primarily on device properties, however, this is no longer the case. Parasitic resistance, capacitance, and inductance associated with interconnections and contacts of an IC are beginning to become increasingly significant factors in IC performance. In current IC technology, the speed limiting factor is no longer device delay, but the resistive-capacitive (RC) delays associated with the conductive interconnections of the IC.
Conventional ICs typically employ an interconnect structure wherein a first conductive line is adjacent a second conductive line. If the capacitance between the first conductive line and the second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second conductive line. This alteration in voltage may result in the IC being inoperable as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information.
FIGS. 1a through 1d illustrate, in simplified, cross-sectional schematic form, a damascene process for forming an inlaid pattern of copper (Cu) metallization features according to conventional practices for manufacture of semiconductor integrated circuit devices. As shown in FIG. 1a, the desired arrangement of conductors is defined as a pattern of recesses 2 such as via holes, grooves, trenches, etc. formed by conventional photolithographic and etching techniques in the surface 4 of a dielectric layer 3 formed over the semiconductor substrate 1. Semiconductor substrate 1 typically comprises a wafer of monocrystalline Si or GaAs, dielectric layer 3 comprises an insulative material typically utilized as an interlevel dielectric (ILD), i.e., an inorganic material such as a silicon oxide, nitride, or oxynitride, or an organic-based or derived material, such as parylene or benzocyclobutene (BCB).
Then, as shown in FIG. 1b, a layer of conductive metal 5, for example, Cu or Cu-based alloy, is deposited by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the recesses 2. In order to ensure complete filling of the recesses, the conductive metal 5 is deposited as a blanket (or “overburden”) layer of excess thickness so as to overfill the recesses 2 and cover the upper surface 4 of the dielectric layer 3. Next, as shown in FIG. 1c, the entire excess thickness t of the overburden layer of conductive metal 5 over the surface of the dielectric layer 3 is removed by a CMP process utilizing, for example, an alumina (A 1203)-based slurry, leaving conductive portions 5′ in the recesses 2 with their exposed upper surfaces 6 substantially co-planar with the surface 4 of the dielectric layer 3.
Referring to FIG. 1d, after removal of the excess thickness t of the overburden layer of conductive metal 5, a barrier layer 7 is deposited before any additional metallization levels are formed. The barrier layer 7 may be used to encapsulate the conductive metal 5 and is typically comprised of a dielectric such as silicon nitride.
The above-described conventional damascene-type process forms inlaid conductors (conductive portions 5′) in the dielectric layer 3 while avoiding problems associated with other types of metallization patterning processing, for example blanket metal layer deposition, followed by photolithographic masking/etching and dielectric gap filling. A variant of the above-described technique, termed “dual damascene” processing, involves the formation of an opening comprising a lower contact or via hole section in communication with an upper groove or trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive via plug in electrical contact with a conductive line. In addition, such single or dual damascene-type processing can be performed with a variety of other types of substrates, for example printed circuit boards, with and/or without intervening dielectric layers, and with a plurality of metallization levels, i.e., five or more levels.
In order to reduce capacitive coupling and therefore reduce capacitive crosstalk, low dielectric constant (“low-K”) materials have been developed to replace conventional dielectric/insulation materials that lie between conductive lines in order to insulate one conductive line from the other. This low-k dielectric material may be used in order to reduce the parasitic capacitance between adjacent conductors.
However, a problem associated with the above-described process is that when a barrier layer composed of a material, for example silicon nitride, which has a relatively high dielectric constant, is blanket-deposited over adjacent conductors as shown in FIG. 1d, it tends to increase the parasitic capacitance between the adjacent conductors. The increased parasitic capacitance due to the deposition over adjacent conductors of a barrier layer comprising silicon nitride thus increases the overall RC time constant of the metallization patterns of the electrical device.
The parasitic capacitance may be reduced by depositing a barrier layer only on the metallization patterns and not on the dielectric material between the metallization patterns. Methods exist for selectively depositing a barrier layer material over metallization features, such as conductive lines. One such method is described in commonly assigned U.S. Pat. No. 6,259,160, incorporated by reference herein for its teachings regarding the formation of a semiconductor device having a selectively fabricated Cu interconnect structure that is encapsulated within selectively formed metallic barriers. A selective metallic capping step comprises depositing a selective electroless metal barrier, preferably comprising Co-W-P (cobalt-tungsten-phosphide), over a Cu interconnect structure.
However, in practice, these methods may not be entirely selective and may undesirably deposit portions of the metal barrier on top of the dielectric between conductive lines. These barrier layer portions are undesirable because they may lead to bridging between conductive lines. This bridging of conductive lines, in turn, may lead to compromised performance or even destruction of the electrical device.
Thus, there exists a need for a metallization process methodology which results in lower inter-line capacitance, and thus produces lower RC time constant metallization patterns, by depositing a metallic barrier by a selective deposition process that is preferential to the metallization patterns, while at the same time substantially eliminating bridging of conductive lines by inter-line metallic barrier portions which may be undesirably produced as a by-product of a selective barrier layer deposition process.
Furthermore, there exists a need for a metallization process methodology which enables formation of damascene structures, for example interconnect and routing lines (particularly of Cu or Cu-based alloys) having high reliability, high product yield, and lower RC time constant metallization patterns.
Moreover, there exists a need for improved metallization processing technology which is fully compatible with conventional process flow, methodology, and throughput requirements in the manufacture of integrated circuit semiconductor devices and other devices requiring inlaid metallization patterns.